Existing semiconductor memories have read circuitry connected between the output data lines of the memory and operable to sense the bit value ("1" or "0") of a selected cell by sensing the voltage differential which has developed across the data lines. When a dynamic sensing amplifier is used as the read circuitry, this voltage differential is sensed after a predetermined time has lapsed from accessing the cell. This predetermined time is controlled by a timing circuit coupled to the read circuitry. It is important to sense reliably a sufficient voltage differential to avoid the risk of bad data being passed to the output; once clocked, a dynamic sense amplifier cannot recover. Conventionally, excessive safety margins are built into the timing chain to avoid this.
In theory it would be possible for the cycle of the timing signal produced by the timing circuit to be predetermined and invariable, based on knowledge of the memory structure and its likely behaviour, i.e. the likely time for a sufficient voltage differential to be developed for sensing. However this is unsatisfactory for several reasons.
Firstly, process tolerances involved in the manufacture of memories mean that any two memories may not have identical behaviour, so that the time required for an adequate differential voltage for sensing by the read circuitry to develop between the data lines may vary from memory to memory. If an invariable timing signal is used, there is the danger that for some memories the timing period will be too short, resulting in bad data being sensed. In other cases it will be longer than is required for the reliable sensing of data thereby unnecessarily slowing down the memory.
Secondly, the behaviour of a semiconductor memory changes in dependence on the environmental conditions, e.g. temperature, in which it operates. Such changes can affect the timing circuit in an adverse manner.
A known arrangement for partially addressing these problems is shown in FIG. 1. In FIG. 1 part of a memory circuit is shown diagrammatically. The memory circuit comprises a plurality of memory cells arranged in rows and columns, all the cells 2 in a row being connected to a common wordline 4 and all the cells in a column being connected between a pair of bit lines 6,8. FIG. 1 also shows precharge transistors 10,12 associated respectively with the bit lines 6,8. Read circuitry and memory output circuitry is indicated diagrammatically by the box 14. The read and output circuitry 14 is controlled by a timing circuit 16.
The timing circuit 16 provides a timing signal .phi. to the read and output circuitry 14 to control the time after accessing a cell at which the voltage differential developed across the bit lines 6,8 is read by the read circuitry. In an attempt to overcome the problems discussed above, the timing signal .phi. produced by the timing circuit 16 is made responsive to the operational conditions of the memory itself by receiving as a control input the voltage developed on a so-called "dummy bit line" 18. The precharge transistors 10,12 serve to precharge the bit lines 6,8 and the dummy bit line 18 to the same predetermined voltage, generally the supply voltage, prior to sensing.
To the dummy bit line 18 are connected a plurality of field effect transistors 20, the gates of which are coupled respectively to the wordlines 4 of the memory array. The drains of the transistors 20 are connected to the dummy bit line 18 and their sources are connected to ground. The transistors 20 act as pull-down devices: whenever a wordline 4 is driven high, the dummy bit line will be discharged through the associated pull-down device.
The timing circuit 16 includes a differential voltage detector which can detect when a predetermined voltage has manifested itself on the dummy bit line. Such differential voltage detectors are known, but operate satisfactorily only with an input voltage at least of the order of 1 or 2 volts. In contrast, the voltage differential across the bit lines might be 200-300 mV. The concept underlying the arrangement of FIG. 1 is that the voltage developed on the dummy bit line 18 should be at a predetermined relationship to the voltage differential developed across the bit lines 6,8 associated with the column of the accessed memory cell. In this way, any changes in the time taken for a satisfactory voltage differential to be developed across the bit lines 6,8 are matched by the voltage developing on the dummy bit line and so the timing circuit is adjusted accordingly.
Although the underlying concept is sound, the implementation shown in FIG. 1 is unsatisfactory. To achieve a situation in which the dummy bit line 18 accurately models the behaviour of the real bit lines 6,8 of the memory array, it is necessary that it should satisfy two criteria:
(a) the capacitance of the dummy bit line must be substantially the same as a real bit line; and PA1 (b) the discharge rate of the dummy bit line should have a predetermined relationship with the discharge rate of a real bit line. PA1 (a) manufacturing as an integrated circuit a plurality of memory cells arranged in rows and columns; PA1 (b) causing connections to be made to said cells such that all the cells in one row are connected to a common memory wordline and the cells in each column are connected between respective pairs of bit lines; PA1 (c) forming a column of dummy cells connected to a dummy bit line, each dummy cell having the same structure as a memory cell; PA1 (d) storing a bit value in a plurality of said dummy cells; and PA1 (e) causing a set of said plurality of dummy cells with a bit value stored therein to be connected to a dummy wordline accessible with said memory wordline.
The simultaneous satisfaction of these two criteria cannot be achieved with the implementation shown in FIG. 1. The capacitance of the real bit lines 6,8 is determined by the size and layout of the transistors in the memory cell 2 (referred to herein as the transistor structure of the cell). Ideally therefore the size of each of the transistors 20 should be as close as possible to the size of a transistor in a memory cell 2. However, even then, a true capacitance match is not achieved since the capacitance of the real bit line is dependant on the layout associated with a real cell and the capacitance of the dummy bit line is dependant on the layout of the single transistor, 20, and these cannot be the same. Further, if transistors of the same size as those in the memory cell are used for the pull-down devices, the discharge rate too will be substantially the same, providing a differential input to the timing circuit of the order of 100 mV, which is difficult to detect. The discharge rate must hence be increased (by increasing the size of the transistors 20) but this further upsets the capacitance match with the real bit line.
A further difficulty arises with the arrangement of FIG. 1 in that the drive characteristics of the transistors 20 do not model the active cells connected to the memory bit lines. The discharge path in a memory cell consists of a pass device in series with a latch device. The pass device is a transistor of small width, with the result that any small offset in width introduced in the manufacturing process gives rise to a large percentage of offset in the drive characteristic of the cell. However, as the transistors 20 have a larger width, the offsets in width introduced by the same manufacturing process will not have the same effect on their drive characteristic.
Also, the factor by which the voltage developed on the dummy bit line multiplies the differential voltage developed across the bit lines 6,8 is predetermined by the size of the transistors 20. If it is desired to change this factor, it may be necessary to change several, perhaps three, masks used during the manufacturing process to make the necessary adjustments to the transistors 20.
An improvement on the arrangement shown in FIG. 1 is illustrated in FIG. 2. For the sake of consistency, the same reference numerals in FIG. 2 represent the same components as in FIG. 1. These components will not be described again. In the embodiment of FIG. 2, the transistors 20 have been replaced by dummy cells 22. These are cells which have the same transistor structure as the memory cells 2 and therefore closely match the capacitance characteristics of the real cells. These dummy cells are rendered inactive by the connection of their wordline to ground.
When a real memory cell 2 is accessed, discharge of the dummy bit line 18 is achieved through a pull-down transistor 24 the gate of which is connected to a dummy wordline 26 which is driven high simultaneously with the accessing wordline 4. While this enables the capacitance of the dummy bit line to match more closely that of the real bit lines, the difficulties relating to the drive characteristics of the pull-down transistor 24 remain unaddressed. There also remains the problem that any changes in timing must be effected by changing the size of the pull-down transistor 24 at the manufacturing stage.
It is not possible therefore with either of the arrangements shown in FIGS. 1 or 2 to provide truly controllable and accurate timing for a memory.